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may 2007 rev 3 1/11 11 dsilc6-4xx esd protection for high speed interface main applications where transient over-voltage protection in esd sensitive equipment is required, such as: computers printers communication systems cell phone handsets and accessories video equipment description the dsilc6-4xx is a monolithic application specific discrete dedicated to esd protection of high speed interfaces, such as usb 2.0, ethernet, display and camera serial interfaces (lvds). the device is ideal for applications where both reduced printed circuit board space and power absorption capability are required. features diode array topology 4 line protection 5 v v cc protection very low capacitance: 1 pf typ. lead-free pacakge rohs compliant benefits very low capacitance between lines to gnd for optimized data integrity low pcb space consumption: 2.9 mm2 max for sot-666 and 1.5 mm2 max for flip-chip cut-off frequency > 2 ghz high reliability offered by monolithic integration mddi, smia, mipi specification compliant functional diagram order code complies with the following standards: part number marking dsilc6-4p6 g DSILC6-4F2 ei iec 61000-4-2 level 4: 8 kv (contact discharge) 15 kv (air discharge) mil std 883g-method 3015-7: class 3b i/o2 i/o3 i/o4 i/o1 vcc gnd flip-chip DSILC6-4F2 sot-666 dsilc6-4p6 i/o3 i/o4 vcc gnd i/o2 i/o1 i/o4 i/o3 gnd vcc i/o1 i/o2 i/o1 i/o4 gnd vcc i/o2 i/o3 flip-chip top-side view flip-chip top-side view sot-666 top-side view www.st.com
characteristics dsilc6-4xx 2/11 1 characteristics table 1. absolute ratings symbol parameter value unit v pp peak pulse voltage iec 61000-4-2 contact discharge iec 61000-4-2 air discharge 8 15 kv i pp peak pulse current i/o to gnd pulse waveform = 8/20 s sot-666 5 a flip-chip 7 p pp peak pulse power sot-666 90 w flip-chip 120 t stg storage temperature range -55 to +150 c t j maximum junction temperature 125 c t l lead solder temperature (10 seconds duration) 260 c table 2. electrical characteristics (t amb = 25 c) symbol parameter v rm reverse stand-off voltage i rm leakage current v br breakdown voltage v f forward voltage v cl clamping voltage i pp peak pulse current symbol parameter test conditions value unit min typ max i rm leakage current v rm = 5 v 0.5 a v br breakdown voltage between v bus and gnd i r = 1 ma 6 v v f forward voltage i f = 10 ma 1 v c i/o-gnd capacitance between i/o and gnd v i/o = 0 v, f = 1 mhz, v osc = 30 mv sot-666 2 2.5 pf flip-chip 2.5 3 v i/o = 1.65 v, v cc = 4.3 v, f = 1 mhz, v osc = 400 mv sot-666 1.5 1.8 flip-chip 1.8 2.0 c i/o-i/o capacitance between i/o v i/o = 0 v, f = 1 mhz, v osc = 30 mv sot-666 1.0 1.25 flip-chip 1.25 1.5 v i/o = 1.65 v, v cc = 4.3 v, f = 1 mhz, v osc = 400 mv sot-666 0.75 0.9 flip-chip 0.9 1.20 c i/o-gnd v i/o = 0 v, f = 1 mhz, v osc = 30 mv 0.06 c i/o-i/o v i/o = 0 v, f = 1 mhz, v osc = 30 mv 0.05
dsilc6-4xx characteristics 3/11 figure 1. relative variation of leakage current versus junction temperature - sot-666 (typical values) figure 2. relative variation of leakage current versus junction temperature flip-chip (typical values) figure 3. remaining voltage after dsilc6-4p6 during esd 15 kv positive surge (air discharge) figure 4. remaining voltage after DSILC6-4F2 during esd 15 kv positive surge (air discharge) figure 5. remaining voltage after dsilc6-4p6 during esd 15 kv negative surge (air discharge) figure 6. remaining voltage after DSILC6-4F2 during esd 15 kv negative surge (air discharge) 1 10 100 25 50 75 100 125 t (c) j v = 5v r i[t rm j ] / i [t rm j =25c] 1 10 100 25 50 75 100 125 t (c) j v= 5v r i[t rm j ] / i [t rm j =25c] 50 ns/div 10 v/div 10 v/div 50 ns/div 50 ns/div 5 v/div 5 v/div 50 ns/div
characteristics dsilc6-4xx 4/11 figure 7. frequency responses of all lines dsilc6-4p6 figure 8. frequency response of all lines DSILC6-4F2 100.0k 1.0m 10.0m 100.0m 1.0g - 20.00 - 15.00 - 10.00 - 5.00 0.00 line 1 line 2 line 3 line 4 f(hz) s21(db) 1.0m 3.0m 10.0m 30.0m 100.0m 300.0m 1.0g 3.0g - 25.00 - 20.00 - 15.00 - 10.00 - 5.00 0.00 s21 (db) line 1 line 2 line 3 line 4 f (hz) figure 9. crosstalk results for lines 1/2 and 1/3 dsilc6-4p6 figure 10. crosstalk results for lines 1/2 and 1/3 DSILC6-4F2 100.0k 1.0m 10.0m 100.0m 1.0g - 140.00 - 120.00 - 100.00 - 80.00 - 60.00 - 40.00 - 20.00 0.00 xtalk 1/2 xtalk 1/3 f(hz) s21(db) 1.0m 3.0m 10.0m 30.0m 100.0m 300.0m 1.0g 3.0g - 140.00 - 120.00 - 100.00 - 80.00 - 60.00 - 40.00 - 20.00 0.00 s21 (db) xtalk 1/2 xtalk 1/3 f (hz)
dsilc6-4xx application examples 5/11 2 application examples 2.1 mddi 2.2 smia analog earpiece audio mddi client & lcd controller chip (with frame buffer) primary lcd secondary lcd lower clamshell upper clamshell hinge mddi data (host) mddi strobe (host) gnd power base band ic data+ data- strobe+ strobe- power gnd dsilc6-4xx smia device data1+ data1- clock+ clock- scl sda esdalc6v1p3 dsilc6-4xx
application examples dsilc6-4xx 6/11 2.3 ethernet 1 gb 2.4 usb 2.0 data transceiver bi_da+ bi_da- bi_db+ bi_db- bi_dc+ bi_dc- bi_dd+ bi_dd- smp75-8 smp75-8 smp75-8 smp75-8 dsilc6-4xx dsilc6-4xx +5v +5v hub- downstream transceiver + 5v r s r s r s r s r pd r pd r pd r pd protecting bus switch device- upstream transceiver + 3.3v sw 1 r pu v bus d+ d- gnd v bus v bus v bus r x ls/fs + r x ls/fs + r x ls/fs + r x ls/fs + r x hs + r x hs + r x hs + r x hs + t x hs + t x hs + t x hs + t x hs + t x ls/fs + t x ls/fs + t x ls/fs + t x ls/fs + r s r s usb connector t x ls/fs - t x ls/fs - t x ls/fs - t x ls/fs - r x ls/fs - r x ls/fs - r x ls/fs - r x ls/fs - r x hs - r x hs - r x hs - r x hs - t x hs - t x hs - t x hs - t x hs - gnd gnd gnd gnd sw 2 device- upstream transceiver dsilc6-4xx usblc6-2p6 usblc6-2sc6 + 3.3v sw 1 r pu v bus d+ d- gnd r s r s usb connector sw 2 open closed then open high speed hs open closed full speed fs closed open low speed ls sw 2 sw 1 mode
dsilc6-4xx ordering information scheme 7/11 3 ordering information scheme dsi lc 6 - 4 xx product designation low capacitance breakdown voltage packages 6 = 6 volts 4 = 4 lines p6 = sot-666 f2 = flip-chip number of lines protected
package information dsilc6-4xx 8/11 4 package information epoxy meets ul94, v0 table 3. sot-666 dimensions ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.45 0.60 0.018 0.024 a3 0.08 0.18 0.003 0.007 b 0.17 0.34 0.007 0.013 b1 0.19 0.27 0.34 0.007 0.011 0.013 d 1.50 1.70 0.059 0.067 e 1.50 1.70 0.059 0.067 e1 1.10 1.30 0.043 0.051 e0.50 0.020 l1 0.19 0.007 l2 0.10 0.30 0.004 0.012 l3 0.10 0.004 figure 11. sot-666 footprint figure 12. sot-666 marking d b l3 l1 e b1 e1 l2 e a a3 0.50 2.60 0.62 0.30 0.99 g
dsilc6-4xx package information 9/11 figure 13. flip-chip dimensions figure 16. flip-chip tape and reel specifications in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 14. flip-chip footprint figure 15. flip-chip marking 1.1 mm 50 m 1.57 mm 50m 500 m 50 315 m 50 500 m 50 650 m 65 copper pad diameter : 220m recommended solder stencil opening : 330m recommended solder mask opening recommendation : 300m recommended x y x w z w e dot, st logo xx = marking yww = datecode (y = year ww = week) z = manufacturing location dot identifying pin a1 location user direction of unreeling all dimensions in mm 4 +/- 0.1 8 +/- 0.3 4 +/- 0.1 1.75 +/- 0.1 3.5 +/- 0.1 ? 1.5 +/- 0.1 0.73 +/- 0.05 xxz yww st e xxz yww st e xxz yww st e
ordering information dsilc6-4xx 10/11 5 ordering information 6 revision history ordering code marking package weight base qty delivery mode dsilc6-4p6 g sot-666 2.9 mg 3000 tape and reel DSILC6-4F2 ei flip-chip 2.22 mg 5000 tape and reel date revision description of changes 10-aug-2006 1 initial release. 04-jan-2007 2 added flip-chip package. added applications examples for smia, ethernet 1 gb, and usb. updated tj max to 150. added v rm line in table 2. modified mddi example figure. 28-may-2007 3 modified functional diagram on page 1 to show top side view instead of bump side view of dsilc64f2. removed v rm line in table 2. added characteristic curves specific to each package for esd, frequency response and crosstalk
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